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Preliminary Technical Data
TIMING SPECIFICATIONS
AC inputs during testing are driven at V SWOUT ? 0.5 V for Logic 1
and 0.45 V for Logic 0. Timing measurements are made at V IH
minimum for Logic 1 and V IL maximum for Logic 0 as shown in
Figure 2.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
ADE7566/ADE7569
float when a 100 mV change from the loaded V OH /V OL level
occurs as shown in Figure 2.
C LOAD for all outputs = 80 pF, unless otherwise noted.
V DD = 2.7 V to 3.6 V; all specifications T MIN to T MAX , unless
otherwise noted.
Table 2. Clock Input (External Clock Driven XTAL1) Parameter
32.768 kHz External Crystal
Parameter
t CK
t CKL
t CKH
t CKR
t CKF
1/t CORE
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency 1
Min
0.032768
Typ Max
30.52
6.26
6.26
9
9
1.024 4.096
Unit
μs
μs
μs
ns
ns
MHz
1
The ADE7566/ADE7569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR.
DV DD – 0.5V
0.45V
0.2DV DD + 0.9V
TEST POINTS
0.2DV DD – 0.1V
V LOAD – 0.1V
V LOAD
V LOAD + 0.1V
TIMING
REFERENCE
POINTS
V LOAD – 0.1V
V LOAD
V LOAD – 0.1V
Figure 2. Timing Waveform Characteristics
Rev. PrA | Page 9 of 136
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